Full 6502 Opcode List Including Undocumented Opcodes ==================================================== File: DOCS.6502.OpList -- Update: 0.10 Author: J.G.Harston - Date: 25-11-1998 This is a complete list of what all the opcodes on the 6502, 65c12 and R65c02 actually do. The 6502 is used in the BBC series computers. The 65c12 is used in the Master series, and the Rockwell R65c02 is used in the 6502 co-processor. nn 6502 65C12 R65C02 -------------------------------------------------------------------------- 00 BRK BRK BRK 01 ORA (zp,X) ORA (zp,X) ORA (zp,X) 02 * HALT * ? * ? 03 * ASL-ORA (zp,X) * ? * ? 04 * NOP zp TSB zp TSB zp 05 ORA zp ORA zp ORA zp 06 ASL zp ASL zp ASL zp 07 * ASL-ORA zp * ? * ? 08 PHP PHP PHP 09 ORA #n ORA #n ORA #n 0A ASL A ASL A ASL A 0B * AND #n/MOV b7->Cy * ? * ? 0C * NOP abs TSB abs TSB abs 0D ORA abs ORA abs ORA abs 0E ASL abs ASL abs ASL abs 0F * ASL-ORA abs * ? BBR 0,zp,rel 10 BPL rel BPL rel BPL rel 11 ORA (zp),Y ORA (zp),Y ORA (zp),Y 12 * HALT ORA (zp) ORA (zp) 13 * ASL-ORA (zp),Y * ? * ? 14 * NOP zp TRB zp TRB zp 15 ORA zp,X ORA zp,X ORA zp,X 16 ASL zp,X ASL zp,X ASL zp,X 17 * ASL-ORA abs,X * ? * ? 18 CLC CLC CLC 19 ORA abs,Y ORA abs,Y ORA abs,Y 1A * NOP INC A INC A 1B * ASL-ORA abs,Y * ? * ? 1C * NOP abs TRB abs TRB abs 1D ORA abs,X ORA abs,X ORA abs,X 1E ASL abs,X ASL abs,X ASL abs,X 1F * ASL-ORA abs,X * ? BBR 1,zp,rel 20 JSR abs JSR abs JSR abs 21 AND (zp,X) AND (zp,X) AND (zp,X) 22 * HALT * ? * ? 23 * ROL-AND (zp,X) * ? * ? 24 BIT zp BIT zp BIT zp 25 AND zp AND zp AND zp 26 ROL zp ROL zp ROL zp 27 * ROL-AND zp * ? * ? 28 PLP PLP PLP 29 AND #n AND #n AND #n 2A ROL A ROL A ROL A 2B * AND #n-MOV b7->Cy * ? * ? 2C BIT abs BIT abs BIT abs 2D AND abs AND abs AND abs 2E ROL abs ROL abs ROL abs 2F * ROL-AND abs * ? BBR 0,zp,rel 30 BMI rel BMI rel BMI rel 31 AND (zp),Y AND (zp),Y AND (zp),Y 32 * HALT AND (zp) AND (zp) 33 * ROL-AND (zp),Y * ? * ? 34 * NOP zp BIT zp,X BIT zp,X 35 AND zp,X AND zp,X AND zp,X 36 ROL zp,X ROL zp,X ROL zp,X 37 * ROL-AND zp,X * ? * ? 38 SEC SEC SEC 39 AND abs,Y AND abs,Y AND abs,Y 3A * NOP DEC A DEC A 3B * ROL-AND abs,Y * ? * ? 3C * NOP abs BIT abs,X BIT abs,X 3D ORA abs,X ORA abs,X ORA abs,X 3E ASL abs,X ASL abs,X ASL abs,X 3F * ROL-AND abs,X * ? BBR 1,zp,rel 40 RTI RTI RTI 41 EOR (zp,X) EOR (zp,X) EOR (zp,X) 42 * HALT * ? * ? 43 * LSR-EOR (zp,X) * ? * ? 44 * NOP zp * ? * ? 45 EOR zp EOR zp EOR zp 46 LSR zp LSR zp LSR zp 47 * LSR-EOR zp * ? * ? 48 PHA PHA PHA 49 EOR #n EOR #n EOR #n 4A LSR A LSR A LSR A 4B * AND #n-LSR A * ? * ? 4C JMP abs JMP abs JMP abs 4D EOR abs EOR abs EOR abs 4E LSR abs LSR abs LSR abs 4F * LSR-EOR abs * ? BBR 0,zp,rel 50 BVC rel BVC rel BVC rel 51 EOR (zp),Y EOR (zp),Y EOR (zp),Y 52 * HALT EOR (zp) EOR (zp) 53 * LSR-EOR (zp),Y * ? * ? 54 * NOP zp * ? * ? 55 EOR zp,X EOR zp,X EOR zp,X 56 LSR zp,X LSR zp,X LSR zp,X 57 * LSR-EOR abs,X * ? * ? 58 CLI CLI CLI 59 EOR abs,Y EOR abs,Y EOR abs,Y 5A * NOP PHY PHY 5B * LSR-EOR abs,Y * ? * ? 5C * NOP abs * ? * ? 5D EOR abs,X EOR abs,X EOR abs,X 5E LSR abs,X LSR abs,X LSR abs,X 5F * LSR-EOR abs,X * ? BBR 1,zp,rel 60 RTS RTS RTS 61 ADC (zp,X) ADC (zp,X) ADC (zp,X) 62 * HALT * ? * ? 63 * ROR-ADC (zp,X) * ? * ? 64 * NOP zp STZ zp STZ zp 65 ADC zp ADC zp ADC zp 66 ROR zp ROR zp ROR zp 67 * ROR-ADC zp * ? * ? 68 PLA PLA PLA 69 ADC #n ADC #n ADC #n 6A ROR A ROR A ROR A 6B * AND #n-ROR A * ? * ? 6C JMP (abs) JMP (abs) JMP (abs) 6D ADC abs ABC abs ADC abs 6E ROR abs ROR abs ROR abs 6F * ROR-ADC abs * ? BBR 0,zp,rel 70 BCS rel BCS rel BCS rel 71 ADC (zp),Y ADC (zp),Y ADC (zp),Y 72 * HALT ADC (zp) ADC (zp) 73 * ROR-ADC (zp),Y * ? * ? 74 * NOP zp STZ zp,X STZ zp,X 75 ADC zp,X ADC zp,X ADC zp,X 76 ROR zp,X ROR zp,X ROR zp,X 77 * ROR-ADC abs,X * ? * ? 78 SEI SEI SEI 79 ADC abs,Y ADC abs,Y ADC abs,Y 7A * NOP PLY PLY 7B * ROR-ADC abs,Y * ? * ? 7C * NOP abs JMP (abs,X) JMP (abs,X) 7D ADC abs,X ADC abs,X ADC abs,X 7E ROR abs,X ROR abs,X ROR abs,X 7F * ROR-ADC abs,X * ? BBR 1,zp,rel 80 * NOP zp BRA rel BRA rel 81 STA (zp,X) STA (zp,X) STA (zp,X) 82 * HALT * ? * ? 83 * STA-STX (zp,X) * ? * ? 84 STY zp STY zp STY zp 85 STA zp STA zp STA zp 86 STX zp STX zp STX zp 87 * STA-STX zp * ? * ? 88 DEY DEY DEY 89 * NOP zp BIT #n BIT #n 8A TXA A TXA TXA 8B * TXA-AND #n * ? * ? 8C STY abs STY abs STY abs 8D STA abs STA abs STA abs 8E STX abs STX abs STX abs 8F * STA-STX abs * ? BBR 0,zp,rel 90 BCC rel BCC rel BCC rel 91 STA (zp),Y STA (zp),Y STA (zp),Y 92 * HALT STA (zp) STA (zp) 93 * STA-STX (zp),Y * ? * ? 94 STY zp STY zp STY zp 95 STA zp,X STA zp,X STA zp,X 96 STX zp,Y STX zp,Y STX zp,Y 97 * STA-STX zp,Y * ? * ? 98 TYA TYA TYA 99 STA abs,Y STA abs,Y STA abs,Y 9A TXS TXS TXS 9B * STA-STX abs,Y * ? * ? 9C * STA-STX abs,X STZ abs * ? 9D STA abs,X STA abs,X STA abs,X 9E * STA-STX abs,X STZ abs,X STZ abs,X 9F * STA-STX abs,X * ? BBR 1,zp,rel A0 LDY #n LDY #n LDY #n A1 LDA (zp,X) LDA (zp,X) LDA (zp,X) A2 LDX #n LDX #n LDX #n A3 * LDA-LDX (zp,X) * ? * ? A4 LDY zp LDY zp LDY zp A5 LDA zp LDA zp LDA zp A6 LDX zp LDX zp LDX zp A7 * LDA-LDX zp * ? * ? A8 TAY TAY TAY A9 LDA #n LDA #n LDA #n AA TAX TAX TAX AB * LDA-LDX * ? * ? AC LDY abs LDY abs LDY abs AD LDA abs LDA abs LDA abs AE LDX abs LDX abs LDX abs AF * LDA-LDX abs * ? BBR 0,zp,rel B0 BCS rel BCS rel BCS rel B1 LDA (zp),Y LDA (zp),Y LDA (zp),Y B2 * HALT LDA (zp) LDA (zp) B3 * LDA-LDX (zp),Y * ? * ? B4 LDY zp LDY zp LDY zp B5 LDA zp,X LDA zp,X LDA zp,X B6 LDX zp,Y LDX zp,Y LDX zp,Y B7 * LDA-LDX zp,Y * ? * ? B8 CLV CLV CLV B9 LDA abs,Y LDA abs,Y LDA abs,Y BA TSX TSX TSX BB * LDA-LDX abs,Y * ? * ? BC LDY abs,X LDY abs,X LDY abs,X BD LDA abs,X LDA abs,X LDA abs,X BE LDX abs,Y LDX abs,Y LDX abs,Y BF * LDA-LDX abs,Y * ? BBR 1,zp,rel C0 CPY #n CPY #n CPY #n C1 CMP (zp,X) CMP (zp,X) CMP (zp,X) C2 * HALT * ? * ? C3 * DEC-CMP (zp,X) * ? * ? C4 CPY zp CPY zp CPY zp C5 CMP zp CMP zp CMP zp C6 DEC zp DEC zp DEC zp C7 * DEC-CMP zp * ? * ? C8 INY INY INY C9 CMP #n CMP #n CMP #n CA DEX DEX DEX CB * SBX #n * ? * ? CC CPY abs CPY abs CPY abs CD CMP abs CMP abs CMP abs CE DEC abs DEC abs DEC abs CF * DEC-CMP abs * ? BBR 0,zp,rel D0 BNE rel BNE rel BNE rel D1 CMP (zp),Y CMP (zp),Y CMP (zp),Y D2 * HALT CMP (zp) CMP (zp) D3 * DEC-CMP (zp),Y * ? * ? D4 * NOP zp * ? * ? D5 CMP zp,X CMP zp,X CMP zp,X D6 DEC zp,X DEC zp,X DEC zp,X D7 * DEC-CMP zp,X * ? * ? D8 CLD CLD CLD D9 CMP abs,Y CMP abs,Y CMP abs,Y DA * NOP PHX PHX DB * DEC-CMP abs,Y * ? * ? DC * NOP abs * ? * ? DD CMP abs,X CMP abs,X CMP abs,X DE DEC abs,X DEC abs,X DEC abs,X DF * DEC-CMP abs,X * ? BBR 1,zp,rel E0 CPX #n CPX #n CPX #n E1 SBC (zp,X) SBC (zp,X) SBC (zp,X) E2 * HALT * ? * ? E3 * INC-SBC (zp,X) * ? * ? E4 CPX zp CPX zp CPX zp E5 SBC zp SBC zp SBC zp E6 INC zp INC zp INC zp E7 * INC-SBC zp * ? * ? E8 INX INX INX E9 SBC #n SBC #n SBC #n EA NOP NOP NOP EB SBC #n SBC #n SBC #n EC CPX abs CPX abs CPX abs ED SBC abs SBC abs SBC abs EE INC abs INC abs INC abs EF * INC-SBC abs * ? BBR 0,zp,rel F0 BEQ rel BEQ rel BEQ rel F1 SBC (zp),Y SBC (zp),Y SBC (zp),Y F2 * HALT SBC (zp) SBC (zp) F3 * INC-SBC (zp),Y * ? * ? F4 * NOP zp * ? * ? F5 SBC zp,X SBC zp,X SBC zp,X F6 INC zp,X INC zp,X INC zp,X F7 * INC-SBC zp,X * ? * ? F8 SED SED SED F9 SBC abs,Y SBC abs,Y SBC abs,Y FA * NOP PLX PLX FB * INC-SBC abs,Y * ? * ? FC * NOP abs * ? * ? FD SBC abs,X SBC abs,X SBC abs,X FE INC abs,X INC abs,X INC abs,X FF * INC-SBC abs,X * ? BBR 1,zp,rel Notes on extra opcodes ---------------------- Opcodes with a * by them in the above list are 'undocumented'. Ones listed as ? are probably the same as the 6502 code, but so far I have not yet tested them. The effects of the opcodes are probably due to the way the instruction logic is decoded within the 65x02. Most instructions do not have full sets of bits turned on, and are of the form xx01 or xx10. This suggests that the bits are used to select the internal function, and so if a bit pattern of xx11 appears, both functions are selected, and both functions get performed. Some instructions do not follow this exactly, as data contension occurs. I have yet to fully find out what, for instance, STA-STX does, as it cannot store both bytes into one byte of memory. As more information comes to light about the exact actions of some opcodes, and as I compile fuller data on the 65c12 and r65c02 I will update this document. Effects of the extra opcodes ---------------------------- HALT - Halts the processor, only a RESET will restart. NOP - Does nothing, may apparently take an address, and so can effectively skips more than just one byte. The addressing modes shown are extrapolated from the other instructions the NOPs appear within. ASL-ORA - Performs an ASL on the data, and then ORAs the result into the A register. AND #n-MOV b7->Cy - ANDs A with the data, and copies bit 7 of A to the Carry flag ROL-AND - Performs a ROL on the data, and then ANDs the result into the A register. LSR-EOR - Performs a LSR on the data, and then EORs the result into the A register ROR-ADC - Performs a ROR on the data, and then ADCs the result into the A register STA-STX - Stores the A register and the X register into memory. I need to test this myself, to find out exactly which or what is stored, as obviously, both cannot be stored TXA-AND #n - Tranfers the X register into the A register, and then ANDs it with #n LDA-LDX - Loads the data into both the A register and the X register DEC-CMP - Decrements the data, and then compares the A register with the result INC-SBC - Increments the data, and then subtracts the result from the A register 6502 Emulators -------------- Most 6502 emulators seem to have chosen &x3 as the opcodes to communicate with the host system, ie the extra (zp,X) addressing mode instructions. Document History ---------------- 25-Nov-1998 v0.10 Initial full version, after months tracking down various sources. References ---------- Undocumented 6502 opcodes: "Extra Instructions Of The 65XX Series CPU" Adam Vardy (abe0084@infonet.st-johns.nf.ca) "Undocumented 6502 opcodes" (mostly from memory), Acorn User article, mid 1980s?. 65c12 and R65c02 opcodes: "The New Advanced User Guide", Dickens & Holmes, Adder, 1987. Undocumented 65c12 and R65c02 opcodes: Investigative research by JGH, 1998.