module kbdenc (
pa[7:0]    , // Slow bus connections
r[7:0]     , // Keyboard row input connections
c[14:0]    , // Keyboard column output 
ca2        , // CA2 output to the System VIA
kben       , // not_Keyboard enable
1mhze      , // Clock
swti       , // Switch input
rsto       , // Reset out
);

//-------------Input Ports-----------------------------
input           pa[3:0]             ; // Column select inputs
input           pa[6:4]             ; // Row select inputs
input           r[7:0]              ; // The keyboard row input connections are normally held high by internal pull-up resistors. If a key is depressed it will cause the appropriate row connection to be pulled low when its column is selected.
input           kben                ; // Generated by the system VIA, this line is taken active low to enable the row and column addresses to be determined by the Operating System
input           1mhze               ; // Timing reference for the positive edge triggered counter and the reset generator circuit.
input           swti                ; // A transition from 5v to 0v or 0v to 5v on this input will cause an active low pulse of 200ms to be generated on pin22 (RSTO).

//-------------Output Ports----------------------------
output          pa7                 ; // This 3-state output provides the ROW data signal to the host system. It is enabled by the nKBEN signal and its output is high if the row address set up on PA4-PA6 points to a row which is at logic low.
output          [14:0] c            ; // These open collector column driving outputs are sequentially taken active low in auto scan mode at a rate of 1 MHz. In polled mode (nKBEN active low), the slow bus inputs PA0 to PA3 determine which output will be low. The selected column output is a direct decode of these inputs.
output          ca2                 ; // Connected to the system VIA, this output will cause the VIA to generate an n IRQ. The line will be active low when an active key is detected.
output          rsto                ; // This open-drain output is triggered by a transition on the Switch Input pin SWTI and provides a logic low output pulse of at least 200mS. For example if SWTI is taken from 0v to 5v via a mechanical switch, the output will immediately fall to 0v, hold low for 200mS after switch bounce and then rise to 5V again.

//-------------Input ports Data Type-------------------
wire		[6:0] pa	; //
wire		[7:0] r		; //
wire		kben		; //
wire		1mhze		; //
wire		swti		; //

//-------------Output Ports Data Type------------------
wire		pa7		; //
reg		[14:0] c	; //
reg		ca2		; //
wire		rsto		; //

assign out = (enable) ? data : 1'bz;

initial begin
	pa[6:0]	= 0;
	r[7:0]	= 0;
	kben	= 0;
	1mhze	= 0;
	swti	= 0;
end

if (kben == 1'b1) begin
	always @ (posedge 1mhze)
	begin : COUNT
		pa[3:0] <= #1 pa[3:0] + 1;
	end
end else begin

end

endmodule					; // End of module KBDENC