A Reset signal from the Tube ULA on pin 37 sends a pulse from p6
of IC26. This resets the CPU and sets the flip flop IC 6.
 
When IC 6 p9 is high (ie, just after RESET) and A15 is high
(>32K), then IC10 p11 is forced low, selecting the ROM. The low
input to IC10 p1 forces the output at p3 high, so deselecting the
RAM.
 
When the CPU reads, the ROM OutputEnable is driven low, so ROM is
read if IC6p9 is high and A15 is high - ie a read >32K just after
RESET.
 
When the CPU writes, the output from IC10p3 is overridden by the
R/W signal through IC10p4/5/6, so writing to RAM.
 
When Tube addresses are selected, IC4p8 goes low, so preventing
IC10p3 from low, so preventing RAM from being accessed. When IC4p8
goes low, the IC6 toggle is reset, so forcing IC6p9 high, so
forcing IC10p11 high so preventing access to ROM.
 
Ah ha. Reads from <32K come from RAM, reads from >32K come from
ROM until the flip flop is reset. Writes always go to RAM. (Except
the Tube registers)
 
I'm not sure why it needed to jump via low memory (other than the
hardware design), as if it continues executing in high memory and
accessed the Tube registers, the ROM would still be paged out and
the CPU would continue executing the same code "underneath" in
RAM.

(JG Harston 2008-03-06 BBC mailing list)